Patent Number: 7,272,052

Title: Decoding circuit for non-binary groups of memory line drivers

Abstract: A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

Inventors: Scheuerlein; Roy E. (Cupertino, CA), Petti; Christopher J. (Mountain View, CA), Fasoli; Luca G. (San Jose, CA)

Assignee: SanDisk 3D LLC

International Classification: G11C 16/06 (20060101)

Expiration Date: 2019-09-18 0:00:00