Patent Number: 7,272,675

Title: First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access

Abstract: Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

Inventors: Paul; Somnath (Fremont, CA), Rekhi; Sanjay (Fremont, CA)

Assignee: Cypress Semiconductor Corporation

International Classification: G06F 3/00 (20060101); G06F 5/00 (20060101); G06F 9/40 (20060101)

Expiration Date: 2019-09-18 0:00:00