Patent Number: 7,272,743

Title: Semiconductor integrated circuit

Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.

Inventors: Oikawa; Kohei (Kamakura, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G06F 1/12 (20060101); G06F 1/04 (20060101); G06F 1/10 (20060101); H04L 7/04 (20060101)

Expiration Date: 2019-09-18 0:00:00