Patent Number: 7,272,805

Title: System and method for converting a flat netlist into a hierarchical netlist

Abstract: System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each hierarchical level of the hierarchical netlist in a top-down fashion, and generating the hierarchical netlist using the set of net collections and the set of cross-coupling capacitor collections.

Inventors: McGaughy; Bruce W. (Fremont, CA), Frey; Peter (San Jose, CA), Krichevskiy; Boris (Sunnyvale, CA)

Assignee: Cadence Design Systems, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-09-18 0:00:00