Patent Number: 7,272,811

Title: Automatic layout method of semiconductor integrated circuit

Abstract: An automatic layout method of a semiconductor integrated circuit includes an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; a placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from a placement so as to improve timing; an placement change restriction calculating step for calculating a placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, a placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.

Inventors: Kurokawa; Keiichi (Hyogo, JP), Yasui; Takuya (Osaka, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-09-18 0:00:00