Patent Number: 7,278,124

Title: Design method for semiconductor integrated circuit suppressing power supply noise

Abstract: An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Inventors: Shimazaki; Kenji (Kobe, JP), Sato; Kazuhiro (Neyagawa, JP), Ichinomiya; Takahiro (Katano, JP), Hirano; Shozo (Osaka, JP), Takahashi; Masao (Takatsuki, JP), Tsujikawa; Hiroyuki (Kusatsu, JP), Kojima; Seijiro (Kyoto, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 17/50 (20060101)

Expiration Date: 2019-10-02 0:00:00