Patent Number: 7,281,180

Title: Memory system and test method therefor

Abstract: A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

Inventors: Furuyama; Takaaki (Kani, JP), Kawamoto; Satoru (Owariasahi, JP)

Assignee: Spansion LLC

International Classification: G11C 29/00 (20060101); G11C 7/00 (20060101)

Expiration Date: 2019-10-09 0:00:00