Patent Number: 7,355,256

Title: MOS Devices with different gate lengths and different gate polysilicon grain sizes

Abstract: A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by a first gate insulating film 24 and a first gate electrode 26 having a first gate length L1 which are stacked, and a second transistor 12 which is formed on the semiconductor substrate 5 and includes a second gate electrode portion 20 constituted by a second gate insulating film 32 and a second gate electrode 30 having a second gate length L2 smaller than the first gate length L1, the second gate insulating film 32 and the second gate electrode 30 being stacked, wherein the grain size of poly-silicon grains forming the first gate electrode 26 is greater than the grain size of poly-silicon grains forming the second gate electrode 30.

Inventors: Togo; Mitsuhiro (Kanagawa, JP), Hasegawa; Eiji (Kanagawa, JP)

Assignee: NEC Electronics Corporation

International Classification: H01L 29/78 (20060101)

Expiration Date: 2020-04-08 0:00:00