Patent Number: 7,355,257

Title: Semiconductor superjunction device

Abstract: A semiconductor superjunction device has a superjunction structure formed in a drift region of the device. The superjunction structure has alternately arranged n-type regions and p-type semiconductor regions layered parallel with the drift direction of carriers, permitting current flow when turned ON and depleting when turned OFF. It also includes a first intrinsic semiconductor region between the n-type and p-type regions. The first intrinsic semiconductor region and the n-type and p-type regions sandwiching the first intrinsic semiconductor region forming a unit. A plurality of units are repetitively arranged to form a repetitively arranged structure. The value of mobility of one of electrons in the n-type region or holes in the p-type region is equal to or less than half the value of mobility of corresponding to one of electrons or holes in the first intrinsic semiconductor region. The superjunction structure eliminates the lower limit that prevents further narrowing of the widths of the n-type and p-type regions to further improve the tradeoff relationship between increasing the breakdown voltage and reducing the on-resistance.

Inventors: Kishimoto; Daisuke (Fukishima, JP), Iwamoto; Susumu (Nagano, JP), Ueno; Katsunori (Nagano, JP)

Assignee: Fuji Electric Holdings Co., Ltd.

International Classification: H01L 31/00 (20060101); H01L 23/58 (20060101)

Expiration Date: 2020-04-08 0:00:00