Patent Number: 7,355,375

Title: Dynamic bias circuit for use with a stacked device arrangement

Abstract: A regulator circuit includes a first transistor coupled to a supply voltage and a second transistor coupled between the first transistor and an output node. The regulator circuit also includes a dynamic bias circuit that may selectively provide a bias voltage to a gate of the second transistor. During a first mode such as a low power mode, for example, the bias circuit may provide the bias voltage at a fixed percentage of the supply voltage as the supply voltage varies. In addition, during a second mode such as a high power mode, for example, the bias circuit may provide the bias voltage at a fixed offset from the supply voltage as the supply voltage varies.

Inventors: Xi; Xiaoyu (Plano, TX)

Assignee: NXP B.V.

International Classification: G05F 1/40 (20060101); G05F 1/56 (20060101)

Expiration Date: 2020-04-08 0:00:00