Patent Number: 7,355,421

Title: Semiconductor apparatus testing arrangement and semiconductor apparatus testing method

Abstract: A semiconductor apparatus testing arrangement for testing a plurality of semiconductor devices produced on a semiconductor substrate, has a substrate on which a plurality of testing units are arranged, each unit comprising a probe needles corresponding to electrode terminals of the semiconductor device and electric conductor parts connected with the probe needles.

Inventors: Maruyama; Shigeyuki (Kawasaki, JP), Arisaka; Yoshikazu (Kawasaki, JP), Tashiro; Kazuhiro (Kawasaki, JP), Katayama; Takayuki (Kawasaki, JP), Ozawa; Tetsu (Kawasaki, JP), Kimura; Yuushin (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G01R 31/02 (20060101); G01R 31/26 (20060101); G06K 5/04 (20060101)

Expiration Date: 2020-04-08 0:00:00