Patent Number: 7,355,433

Title: Configurations and method for carrying out wafer level unclamped inductive switching (UIS) tests

Abstract: This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET. Furthermore, the test circuit further includes a timing and make before break (MBB) circuit for receiving an MOSFET failure signal from the MOSFET failure detection circuit and for controlling the first and second switches for switching off a power supply to the MOSFET device upon a detection of an UIS failure under the UIS test to prevent damages to a probe

Inventors: Lui; Sik K (Sunnyvale, CA), Bhalla; Anup (Santa Clara, CA)

Assignee: Alpha & Omega Semiconductor, Ltd

International Classification: G01R 31/26 (20060101); G01R 31/28 (20060101)

Expiration Date: 2020-04-08 0:00:00