Patent Number: 7,355,881

Title: Memory array with global bitline domino read/write scheme

Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Inventors: Dankert; Floyd L. (Austin, TX), Andrade; Victor F. (Austin, TX), Posey; Randal L. (Austin, TX), Ciraula; Michael K. (Round Rock, TX), Schaefer; Alexander W. (Austin, TX), Moench; Jerry D. (Austin, TX), Chrudimsky; Soolin Kao (Austin, TX), Braganza; Michael C. (Austin, TX), Huber; Jan Michael (Austin, TX), Novak; Amy M. (Austin, TX)

Assignee: Advanced Micro Devices, Inc.

International Classification: G11C 11/00 (20060101); G11C 7/00 (20060101); G11C 7/10 (20060101)

Expiration Date: 2020-04-08 0:00:00