Patent Number: 7,356,451

Title: Assertion handling for timing model extraction

Abstract: Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.

Inventors: Moon; Cho Woo (San Diego, CA), Kriplani; Harish (Saratoga, CA), Belkhale; Krishna Prasad (Saratoga, CA)

Assignee: Cadence Design Systems, Inc.

International Classification: G06F 17/50 (20060101); G06F 9/45 (20060101)

Expiration Date: 2020-04-08 0:00:00