Patent Number: 7,466,160

Title: Shared memory bus architecture for system with processor and memory units

Abstract: A system is provided for testing a first integrated circuit associated with at least a second integrated circuit in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and second integrated circuits, and wherein the first integrated circuit is designed for normal operation and a test mode. The system includes a plurality of multiplexer circuits. Each multiplexer circuit is operable to receive a respective signal from the second integrated circuit when the first integrated circuit is in normal operation. Each multiplexer circuit is further operable to receive a respective signal from either the second integrated circuit or an associated external terminal when the first integrated circuit is in test mode. An external terminal of the semiconductor device operable to receive a signal for causing the first integrated circuit to transition between normal operation and the test mode.

Inventors: Ong; Adrian E. (Pleasanton, CA), Baliga; Naresh (El Dorado, CA), Lin; Chiate (San Jose, CA)

Assignee: Inapac Technology, Inc.

International Classification: G01R 31/28 (20060101); G11C 29/00 (20060101); G11C 7/00 (20060101)

Expiration Date: 2021-12-16 0:00:00