Patent Number: 7,535,084

Title: Multi-chip package with a single die pad

Abstract: A multi-chip package with a single die pad is provided. The multi-chip package includes a leadframe having a die pad and a plurality of leads surrounding the die pad. Each of the leads includes an upper lead, a lower lead and an intermediate lead substantially perpendicularly connected to the upper and lower leads, wherein the upper and lower leads are substantially parallel to the die pad. The upper and lower surfaces of the die pad are attached with upper and lower chips respectively. The upper chip is electrically connected to the upper surface of one part of the upper leads by a plurality of first bonding wires and the lower chip is electrically connected to the lower surfaces of the other part of the upper leads by a plurality of second bonding wires. A sealant is used to encapsulate the chips and bonding wires to protect these elements from damage.

Inventors: Kim; Hong Hyoun (Kyunggi-do, KR)

Assignee: Advanced Semiconductor Engineering, Inc.

International Classification: H01L 23/495 (20060101)

Expiration Date: 2021-05-19 0:00:00