Patent Number: 7,535,113

Title: Reduced inductance in ball grid array packages

Abstract: Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within the BGA package is in the wire bonds that couple the set of contacts to the IC. The techniques described herein shorten the wire bonds in order to reduce the amount of parasitic inductance. The techniques include extending traces from a subset of the contacts inward into the BGA package toward the IC mounted. The wire bonds then couple the traces to the IC, thereby electrically coupling the subset of contacts to the IC. The presence of the traces substantially reduces lengths of the wire bonds relative to wire bonds that directly couple the set of contacts to the IC.

Inventors: Kramer; Allen N. (Hudson, WI)

Assignee: Seagate Technology LLC

International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101)

Expiration Date: 2021-05-19 0:00:00