Patent Number: 7,535,259

Title: Clocked inverter, NAND, NOR and shift register

Abstract: A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source.

Inventors: Osame; Mitsuaki (Atsugi, JP), Anzai; Aya (Tsukui, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

International Classification: H03K 19/20 (20060101)

Expiration Date: 2021-05-19 0:00:00