Patent Number: 7,535,271

Title: Locked loop circuit with clock hold function

Abstract: A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.

Inventors: Kizer; Jade M. (Mountain View, CA)

Assignee: Rambus Inc.

International Classification: H03L 7/06 (20060101)

Expiration Date: 2021-05-19 0:00:00