Patent Number: 7,535,275

Title: High-performance memory interface circuit architecture

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Inventors: Huang; Joseph (San Jose, CA), Sung; Chiakang (Milpitas, CA), Pan; Philip (Fremont, CA), Chong; Yan (San Jose, CA), Lee; Andy L. (San Jose, CA), Johnson; Brian D. (Issaquah, WA)

Assignee: Altera Corporation

International Classification: H03L 7/00 (20060101)

Expiration Date: 2021-05-19 0:00:00