Patent Number: 7,535,689

Title: Reducing input capacitance of high speed integrated circuits

Abstract: An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity is formed underneath the pad.

Inventors: Zeng; Xiang Yin (Shanghai, CN), Cui; Ming Dong (Shanghai, CN), Christensen; Gregory V. (Lehi, UT), Abdulla; Mostafa Naguib (Rancho Cordova, CA), Lu; Daoqiang (Chandler, AZ), He; Jiangqi (Gilbert, AZ), Tang; Jiamiao (Shanghai, CN)

Assignee: Intel Corporation

International Classification: H02H 9/00 (20060101); H02H 1/00 (20060101)

Expiration Date: 2021-05-19 0:00:00