Patent Number: 7,535,741

Title: Semiconductor device

Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET for a high-side switch and a power MOS.cndot.FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS.cndot.FET for the high-side switch is formed by a p channel vertical MOS.cndot.FET, and the power MOS.cndot.FET for the low-side switch is formed by an n channel vertical MOS.cndot.FET. Thus, a semiconductor chip formed with the power MOS.cndot.FET for the high-side switch and a semiconductor chip formed with the power MOS.cndot.FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.

Inventors: Shiraishi; Masaki (Hitachinaka, JP), Akiyama; Noboru (Hitachinaka, JP), Uno; Tomoaki (Takasaki, JP), Matsuura; Nobuyoshi (Takasaki, JP)

Assignee: Renesas Technology Corp.

International Classification: H02M 1/00 (20070101); H01L 23/48 (20060101); H05K 7/02 (20060101)

Expiration Date: 2021-05-19 0:00:00