Patent Number: 7,535,762

Title: Semiconductor memory device

Abstract: A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Inventors: Tanaka; Tomoharu (Yokohama, JP), Nakamura; Hiroshi (Kawasaki, JP), Tanzawa; Toru (Ebina, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 16/04 (20060101)

Expiration Date: 2021-05-19 0:00:00