Patent Number: 7,611,960

Title: Method and system for wafer backside alignment

Abstract: Disclosed is a method and a system for wafer backside alignment. A zero mark patterning on front side of a substrate. A plurality of layers are deposited on the front side of the substrate. The wafer is flipped over with backside of the substrate facing up, and a through wafer etching is performed from the backside to an etch stop layer deposited over the front side of the substrate.

Inventors: Liu; Sheng-Chieh (Taichung, TW), Kao; Chia-Hung (Hsin-Chu, TW), Wu; Tzu-Yang (Hsin-Chu, TW), Pan; Sheng-Liang (Hsin-Chu, TW), Lee; Yuan-Bang (Miaoli County, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H01L 21/76 (20060101); H01L 21/302 (20060101); H01L 21/461 (20060101)

Expiration Date: 1/03/02017