Patent Number: 7,612,391

Title: Semiconductor integrated circuit device

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefore for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Inventors: Kanno; Yusuke (Tokyo, JP), Mizuno; Hiroyuki (Tokyo, JP), Irie; Naohiko (Tokyo, JP)

Assignee: Renesas Technology Corp.

International Classification: H01L 23/50 (20060101)

Expiration Date: 1/03/02017