Patent Number: 7,612,397

Title: Memory cell having first and second capacitors with electrodes acting as control gates for nonvolatile memory transistors

Abstract: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Inventors: Ueda; Naoki (Nara, JP), Yamauchi; Yoshimitsu (Nabari, JP)

Assignee: Sharp Kabushiki Kaisha

International Classification: H01L 27/108 (20060101); H01L 29/00 (20060101); H01L 29/76 (20060101); H01L 29/94 (20060101); H01L 31/119 (20060101)

Expiration Date: 1/03/02017