Patent Number: 7,612,406

Title: Transistor, memory cell array and method of manufacturing a transistor

Abstract: A transistor includes a first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode to control an electrical current flowing in the channel. The gate electrode is disposed in a gate groove, the gate groove being defined in a top surface of a semiconductor substrate. The first and second source/drain regions extend at least to a depth d1, the depth d1 being measured from the top surface of the substrate. A top surface of the gate electrode is disposed beneath the top surface of the semiconductor substrate. A top surface of the gate electrode is disposed at a depth d2 which is less than the depth d1, the depth d2 being measured from the substrate surface.

Inventors: Kluge; Johannes von (Dresden, DE)

Assignee: Infineon Technologies AG

International Classification: H01L 29/768 (20060101)

Expiration Date: 1/03/02017