Patent Number: 7,612,414

Title: Overlapped stressed liners for improved contacts

Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

Inventors: Chen; Xiangdong (Poughquag, NY), Kim; Jun Jung (Paju, KR), Ko; Young Gun (Kyunggi-do, KR), Park; Jae-Eun (Fishkill, NY), Yang; Haining S. (Wappingers Falls, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/8238 (20060101); H01L 23/18 (20060101)

Expiration Date: 1/03/02017