Patent Number: 7,612,574

Title: Systems and methods for defect testing of externally accessible integrated circuit interconnects

Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.

Inventors: Fujiwara; Yoshinori (Tsukuba, JP), Nomura; Masayoshi (Ryugasaki, JP)

Assignee: Micron Technology, Inc.

International Classification: G01R 31/28 (20060101); G01R 31/04 (20060101)

Expiration Date: 1/03/02017