Patent Number: 7,612,599

Title: Semiconductor device

Abstract: Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.

Inventors: Motoyoshi; Minoru (Ome, JP), Fujimura; Yasuhiro (Hamura, JP), Nakahara; Shigeru (Higashiyamato, JP)

Assignee: Hitachi, Ltd.

International Classification: H03K 3/00 (20060101)

Expiration Date: 1/03/02017