Patent Number: 7,613,032

Title: Semiconductor memory device and control method thereof

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

Inventors: Yabe; Tomoaki (Kawasaki, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 11/00 (20060101)

Expiration Date: 1/03/02017