Patent Number: 7,613,057

Title: Circuit and method for a sense amplifier

Abstract: A circuit and method for providing a sense amplifier for a DRAM memory with reduced distortion in a control signal, the sense amplifier particularly useful for embedding DRAM memory with other logic and memory functions in an integrated circuit. A sense enable circuit is provided for a differential sensing latch in a sense amplifier having a cascade coupled pair of transistors, each transistor receiving a separate control signal. The separate control signals are provided by a control circuit with a delayed overlap. Differential sensing is enabled when the delayed overlap exists between the separate control signals. An array of DRAM memory cells are coupled to a plurality of the sense amplifiers. The DRAM memory incorporating the sense amplifiers may be embedded with other circuitry in an integrated circuit. Methods for providing the control signals and for laying out the DRAM memory with the sense amplifiers are provided.

Inventors: Lee; Cheng Hung (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: G11C 7/00 (20060101)

Expiration Date: 1/03/02017