Patent Number: 7,613,211

Title: Digital clock smoothing apparatus and method

Abstract: A method for digital clock smoothing comprising: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a two-port memory block; (B) accumulating a plurality of symbols of the asynchronous data stream in the two-port memory block for a predetermined time period; (C) computing an average symbol rate for the input asynchronous data stream; (D) generating a clock error signal equal to the difference between the average symbol rate of the input asynchronous data stream and a nominal output synchronous clock; (E) obtaining a smoothed symbol rate clock by using the error clock signal; and (F) generating an output smoothed data stream having the smoothed symbol rate clock.

Inventors: Fagerlund; Richard John (San Jose, CA), Flynn; James P. (Palo Alto, CA), Fong; Mark (San Jose, CA), Isaksen; David Bruce (Mountain View, CA)

Assignee: Wideband Semiconductors, Inc.

International Classification: H04J 3/06 (20060101); H04L 7/00 (20060101)

Expiration Date: 1/03/02017