Patent Number: 7,613,856

Title: Arbitrating access for a plurality of data channel inputs with different characteristics

Abstract: A configurable buffer arbiter is provided that combines a time-slot based algorithm, a fairness-based algorithm, and a priority-based algorithm to meet the bandwidth and latency requirements of multiple channels needing access to a buffer memory. The channels have different static and dynamic characteristics. The static channel characteristics include aspects such as a required latency for access to the buffer memory, a required bandwidth to the buffer memory, a preferred latency or bandwidth to the buffer memory, the amount of data the channel can burst in each access to the buffer memory, and the ability for the channel to continuously burst its data to the buffer memory with or without any pauses. The dynamic characteristics include aspects such as whether a channel's FIFO is nearing full or empty, or whether one of the static characteristics has suddenly become more critical. Configuration of the arbiter algorithms exists to optimize the arbiter for both the static and dynamic channel characteristics.

Inventors: Kastein; Kurt Jay (Fort Collins, CO), Ellis; Jackson Lloyd (Fort Collins, CO), Arntzen; Eskild Thormod (Cheyenne, WY)

Assignee: LSI Corporation

International Classification: G06F 13/12 (20060101); G06F 13/38 (20060101); H04J 3/02 (20060101); H04L 12/43 (20060101)

Expiration Date: 1/03/02017