Patent Number: 7,613,859

Title: Back-off timing mechanism in a digital signal processor

Abstract: Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

Inventors: Asano; Shigehiro (Yokosuka, JP), Ishii; Tsutomu (Tokyo, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G06F 13/00 (20060101)

Expiration Date: 1/03/02017