Patent Number: 7,613,885

Title: Cache coherency control method, chipset, and multi-processor system

Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.

Inventors: Uehara; Keitaro (Kokubunji, JP), Okitsu; Jun (Kokubunji, JP), Murakami; Yoshiki (Hadano, JP)

Assignee: Hitachi, Ltd.

International Classification: G06F 12/00 (20060101)

Expiration Date: 1/03/02017