Patent Number: 7,613,960

Title: Semiconductor device test apparatus and method

Abstract: There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or not on the basis of a response signal, and uses a repair analysis computing unit to analyze the result of the test to determine how to replace a defective cell of the memory with a spare line. The repair analysis computing unit includes a fail memory which stores test results and a general-purpose repair analysis part which analyzes the test results in accordance with an MRA program and inserts and executes a user function of a user analysis program between units of analysis processing.

Inventors: Okawa; Kazuyoshi (Tokyo, JP), Ogino; Junko (Tokyo, JP), Yoshinaga; Masayuki (Tokyo, JP), Honda; Hajime (Tokyo, JP)

Assignee: Advantest Corporation

International Classification: G11C 29/00 (20060101)

Expiration Date: 1/03/02017