Patent Number: 7,613,968

Title: Device and method for JTAG test

Abstract: In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two devices such as a JTAG test supported device and a JTAG test unsupported device, boundary scan FFs are inserted between the two devices to be combined with another device configured in the same way and the JTAG test unsupported parts of both devices are equivalently combined to be regarded as one JTAG test unsupported device. Then, this device is sandwiched by the JTAG test supported devices and a JTAG test is conducted.

Inventors: Ishikawa; Katsuya (Kawasaki, JP)

Assignee: Fujitsu Microelectronics Limited

International Classification: G01R 31/28 (20060101); G01R 27/28 (20060101); G01R 31/00 (20060101); G11C 29/00 (20060101); G06F 17/50 (20060101); G01R 31/14 (20060101)

Expiration Date: 1/03/02017