Patent Number: 7,709,365

Title: CMOS well structure and method of forming the same

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Inventors: Haensch; Wilfried (Somers, NY), Hook; Terence B. (Jericho Center, VT), Hsu; Louis C. (Fishkill, NY), Joshi; Rajiv V. (Yorktown Heights, NY), Rausch; Werner (Stormville, NY)

Assignee: International Business Machines Corporation

International Classification: H01L 21/22 (20060101); H01L 21/38 (20060101)

Expiration Date: 5/04/12018