Patent Number: 7,709,396

Title: Integral patterning of large features along with array using spacer mask patterning process flow

Abstract: Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.

Inventors: Bencher; Christopher Dennis (San Jose, CA), Tang; Jing (Cupertino, CA)

Assignee: Applied Materials, Inc.

International Classification: H01L 21/302 (20060101)

Expiration Date: 5/04/12018