Patent Number: 7,709,827

Title: Vertically integrated field-effect transistor having a nanostructure therein

Abstract: The invention relates to a vertical integrated component, a component arrangement and a method for production of a vertical integrated component. The vertical integrated component has a first electrical conducting layer, a mid layer, partly embodied from dielectric material on the first electrical conducting layer, a second electrical conducting layer on the mid layer and a nanostructure integrated in a through hold introduced in the mid layer. A first end section of the nanostructure is coupled to the first electrical conducting layer and a second end section is coupled to the second electrical conducting layer. The mid layer includes a third electrical conducting layer between two adjacent dielectric partial layers, the thickness of which is less than the thickness of at least one of the dielectric partial layers.

Inventors: Graham; Andrew (Munchen, DE), Hofmann; Franz (Munchen, DE), Honlein; Wolfgang (Unterhaching, DE), Kretz; Johannes (Munchen, DE), Kreupl; Franz (Munchen, DE), Landgraf; Erhard (Munchen, DE), Luyken; Johannes Richard (Munchen, DE), Rosner; Wolfgang (Ottobrunn, DE), Schulz; Thomas (Austin, TX), Specht; Michael (Munchen, DE)

Assignee: Qimonda, AG

International Classification: H01L 21/8238 (20060101)

Expiration Date: 5/04/12018