Patent Number: 7,709,942

Title: Semiconductor package, including connected upper and lower interconnections

Abstract: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.

Inventors: Jobetto; Hiroyasu (Hachioji, JP)

Assignee: Casio Computer Co., Ltd.

International Classification: H01L 23/02 (20060101)

Expiration Date: 5/04/12018