Patent Number: 7,710,172

Title: DLL circuit, semiconductor memory device using the same, and data processing system

Abstract: A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

Inventors: Kuroki; Koji (Tokyo, JP), Takai; Yasuhiro (Tokyo, JP), Fujisawa; Hiroki (Tokyo, JP)

Assignee: Elpida Memory, Inc.

International Classification: H03L 7/06 (20060101)

Expiration Date: 5/04/12018