Patent Number: 7,710,186

Title: Averaging circuit apparatus, error signal generation system and method of averaging an error signal

Abstract: An averaging circuit apparatus comprises a rectifier having an input for receiving a high-speed error signal having, for example, a data rate of 10 Gbps. An integrator is coupled to the rectifier and has an error output for providing an averaged representation of the error signal. The averaged representation of the error signal is supplied to a Digital Signal Processor in a channel equalizer loop for equalizing a fiber-optic channel. The Digital Signal Processor executes an algorithm that sets tap coefficients of an analogue filter in response to the averaged representation of the error signal.

Inventors: Aboulhouda; Samir (Ipswich, GB), Seifu; Fesseha Tessera (London, GB)

Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.

International Classification: G06F 7/42 (20060101)

Expiration Date: 5/04/12018