Patent Number: 7,710,761

Title: CMOS SRAM/ROM unified bit cell

Abstract: A memory cell including a bit and bitnot sense lines as well as a random access memory (RAM) word line and a read only memory (ROM) word line. The memory cell particularly includes a static RAM (SRAM) bit cell and a ROM bit cell. The SRAM bit cell is coupled between the bit and bitnot sense lines, and is responsive to a signal on the RAM word line. The ROM bit cell is also coupled between the bit and bitnot sense lines, and is responsive to a signal on the ROM word line. The ROM bit cell includes first and second ROM pass transistors, a first node for permanently programming connection of the first ROM pass transistor to either a voltage line or a ground line, and a second node for permanently programming connection of the second ROM pass transistor to either the voltage line or the ground line.

Inventors: Miller; Dennis Ray (Chandler, AZ), Rahman; Mohammad Hafijur (Gilbert, AZ), Kabir; Mohammad Ehsanul (San Jose, CA)

Assignee: VNS Portfolio LLC

International Classification: G11C 11/00 (20060101)

Expiration Date: 5/04/12018