Patent Number: 7,710,785

Title: Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers

Abstract: A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage.

Inventors: Ohsawa; Takashi (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G11C 16/04 (20060101); H01L 27/01 (20060101)

Expiration Date: 5/04/12018