Patent Number: 7,711,010

Title: Phase-locked loop for maintaining system synchronization through packet dropout

Abstract: A phase-locked loop for maintaining system synchronization of a receiver with a transmitter through packet dropout. A clock signal is generated by an oscillator and the interval between the neighboring pieces of incoming system timing information is determined by a first packet counter. A second packet counter determines the interval between neighboring timing signals generated by the first packet counter. Two count values of the system timing information are retained by a delay buffer. In accordance with a value of comparison which is obtained by a difference circuit from the difference between the two count values and is larger or smaller than an error expected on system synchronization, the counter value is corrected by an overflow corrector. A cumulative offset of the clock position is corrected by a phase difference detector. The corrected offset is integrated by an integrator only at a timing of the system timing information incoming.

Inventors: Akahori; Hiroji (Tokyo, JP)

Assignee: Oki Semiconductor Co., Ltd.

International Classification: H04J 3/06 (20060101)

Expiration Date: 5/04/12018