Patent Number: 7,711,077

Title: System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Inventors: Agazzi; Oscar E. (Irvine, CA), Kruse; David (Newport Beach, CA), Abnous; Arthur (Irvine, CA), Hatamian; Mehdi (Mission Viejo, CA)

Assignee: Broadcom Corporation

International Classification: H04B 1/10 (20060101); H03D 1/06 (20060101)

Expiration Date: 5/04/12018