Patent Number: 7,711,535

Title: Simulation of hardware and software

Abstract: A method and apparatus are provided to allow co-verification of hardware and software elements asynchronously from a programmable logic device (PLD).

Inventors: Brookes; Peter (Reading, GB), Hall; Andrew (High Wycombe, GB), Gray; Nigel (High Wycombe, GB)

Assignee: Altera Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 5/04/12018