Patent Number: 7,711,930

Title: Apparatus and method for decreasing the latency between instruction cache and a pipeline processor

Abstract: A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

Inventors: Dieffenderfer; James N. (Apex, NC), Doing; Richard W. (Raleigh, NC), Stempel; Brian M. (Raleigh, NC), Testa; Steven R. (Durham, NC), Tsuchiya; Kenichi (Cary, NC)

Assignee: International Business Machines Corporation

International Classification: G06F 9/30 (20060101); G06F 9/38 (20060101)

Expiration Date: 5/04/12018